Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Base implementation of the MMU + TLB + Exceptions #4

Open
wants to merge 14 commits into
base: master
Choose a base branch
from

Conversation

dignifiedquire
Copy link
Collaborator

Based on #3

This is my first attempt at implementing these things. It's a lot of code, lots of feedback very welcome.

Correctness, unsure, my test roms are doing much more than before :)

  • tlb fetch -> miss -> fill cycles do work, in my test roms
  • if all addressing is fully correct I am still trying to verify

@@ -567,7 +862,10 @@ impl Cpu {
self.ctx.tight_exit = false;
while let Some(op) = iter.next() {
self.ctx.pc += 4;
self.op(op);
match self.op(op) {
Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

quick comment, this adds a cmp+branch on any opcode. This loop here is hot as fire, I think it's better to let the opcode implementation call exception() whenever an exception occurs, rather than propagate a Result and then having to check it for every opcode.

@@ -88,7 +127,176 @@ pub struct CpuContext {
lines: Lines,
}

#[derive(DeviceBE)]
pub struct RegsMI {
Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think MI is strictly part of MIPS64. MI is a Nintendo part that handle memory mapping and it's behavior is strictly n64-related. FWIW, src/mips64 tries to be a generic MIPS interpreter, not directly related to N64.

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The MIPS Interface is part of the Reality Coprocessor.
image
image
In both the patent and an SGI presentation, the MI is referred to as the CPU interface, but it is the MI.
All the interfaces you see in these screenshots are part of the RCP.
In my emulator, I even moved the memory map definition into the RCP and connected the VR4300's SysAD reads and writes to it.

Copy link

@Nabile-Rahmani Nabile-Rahmani Dec 1, 2018

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Regarding the SysAD, I simplified the whole protocol into read and write word delegates, even though it has its own set of commands the CPU and external SysAD device (the RCP) use to communicate.

Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

That's fine, but this PR is adding the MI within a generic MIPS64 interpreter, not within the RCP code.

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yep, I noticed that, hence saying it's part of the RCP.
https://github.com/rasky/r64/blob/master/src/n64.rs#L29-L35 also shows that the other RCP interfaces (and the SP/DP) are defined within the n64 struct, when they technically should be part of a rcp struct.
Sorry if I'm too pedantic :p

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants